As the technology scales down to very deep submicron the vulnerability of integrated circuits to soft errors increase remarkably. Soft errors caused by high energy particles striking the substrate of integrated circuits increase as the chip density, clock frequency, and voltage supply change due to technology development. Therefore, fault-tolerance mechanisms become more essential in both combinational and sequential circuits. The goal for fault-tolerant designs is achieving a reliable system by detecting soft errors while reducing the area and power consumption.
- Yu Q, Stock D. Collaborative error control method for sequential logic circuits, in 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). ; 2013 :785-788.
- Pahlevanzadeh H, Yu Q. A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients. Journal of Electronic Testing. 2014;30 :595-609.
- Pahlevanzadeh H, Yu Q. Systematic analyses for latching probability of single-event transients, in Fifteenth International Symposium on Quality Electronic Design. ; 2014 :442-449.
- Nsengiyumva P, Yu Q. Investigation of single-event upsets in dynamic logic based flip-flops, in 2015 IEEE International Symposium on Circuits and Systems (ISCAS). ; 2015 :818-821.