Sunkavilli S, Zhang Z, Yu Q. Analysis of Attack Surfaces and Practical Attack Examples in Open Source FPGA CAD Tools, in 2021 22nd International Symposium on Quality Electronic Design (ISQED). ; 2021 :504-509.
Zhang Z, Miketic I, Salman E, Yu Q. Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking, in Proceedings of the 2021 on Great Lakes Symposium on VLSI. New York, NY, USA: Association for Computing Machinery ; 2021 :415-420. Publisher's VersionAbstract
Logic locking has demonstrated its potential to protect the intellectual property of integrated circuits (ICs). The security strength of logic locking is typically evaluated through functional and structural analysis-based attacks. There is limited work analyzing logic locking techniques' resilience against power-based side-channel attacks. To fill this gap, we propose an attack flow for the correlation power analysis (CPA) attack on the circuits encrypted with transistor-level logic locking. Our case studies indicate that CPA attacks outperform DPA attacks in terms of key recovery rate (KRR). To improve the CPA attack resilience of an existing transistor-level logic locking technique, we propose a logic-cone conjunction (LCC) method to enlarge the key space and reduce the correlation between the locking key and the power consumption of locked circuits. The experimental results show that the LCC method successfully reduces the KRR from 100% to 0% by using cyclic logic structures. The FPGA emulation indicates that the proposed method incurs 2.6% more delay and 1.5% more power consumption than the baseline.
Xu D, Liu B, Feng W, Ming J, Zheng Q, Li J, Yu Q. Boosting SMT Solver Performance on Mixed-Bitwise-Arithmetic Expressions, in Proceedings of the 42nd ACM SIGPLAN International Conference on Programming Language Design and Implementation. New York, NY, USA: Association for Computing Machinery ; 2021 :651–664. Publisher's VersionAbstract
Satisfiability Modulo Theories (SMT) solvers have been widely applied in automated software analysis to reason about the queries that encode the essence of program semantics, relieving the heavy burden of manual analysis. Many SMT solving techniques rely on solving Boolean satisfiability problem (SAT), which is an NP-complete problem, so they use heuristic search strategies to seek possible solutions, especially when no known theorem can efficiently reduce the problem. An emerging challenge, named Mixed-Bitwise-Arithmetic (MBA) obfuscation, impedes SMT solving by constructing identity equations with both bitwise operations (and, or, negate) and arithmetic computation (add, minus, multiply). Common math theorems for bitwise or arithmetic computation are inapplicable to simplifying MBA equations, leading to performance bottlenecks in SMT solving. In this paper, we first scrutinize solvers' performance on solving different categories of MBA expressions: linear, polynomial, and non-polynomial. We observe that solvers can handle simple linear MBA expressions, but facing a severe performance slowdown when solving complex linear and non-linear MBA expressions. The root cause is that complex MBA expressions break the reduction laws for pure arithmetic or bitwise computation. To boost solvers' performance, we propose a semantic-preserving transformation to reduce the mixing degree of bitwise and arithmetic operations. We first calculate a signature vector based on the truth table extracted from an MBA expression, which captures the complete MBA semantics. Next, we generate a simpler MBA expression from the signature vector. Our large-scale evaluation on 3000 complex MBA equations shows that our technique significantly boost modern SMT solvers' performance on solving MBA formulas.
Zhang Z, Miketic I, Salman E, Yu Q. Towards Enhancing Power-Analysis Attack Resilience for Logic Locking Techniques, in 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). ; 2021 :132-137.
Sunkavilli S, Zhang Z, Yu Q. New Security Threats on FPGAs: From FPGA Design Tools Perspective, in 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). ; 2021 :278-283.
Yellu P, Buell L, Mark M, Kinsy M, Xu D, Yu Q. Security Threat Analyses and Attack Models for Approximate Computing Systems: From Hardware and Micro-Architecture Perspectives. Transactions on Design Automation of Electronic Systems [Internet]. 2021;26 (4) :Article 32. Publisher's Version
Wara MS, Yu Q. New Replay Attacks on Zigbee Devices for Internet-of-Things (IoT) Applications, in 16th IEEE International Conference on Embedded Software and Systems (ICESS'20). Online: IEEE ; 2020.
Zhang Z, Dofe J, Yu Q. Comprehensive Analysis on Hardware Trojans in 3D ICs: Characterization and Experimental Impact Assessment. Springer Nature Computer Science [Internet]. 2020;(1) :1-13. Publisher's Version
Zhang Z, Yu Q. FTAI: Frequency-based Trojan-Activity Identification Method for 3D Integrated Circuits, in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'20). Springfield, MA, USA: IEEE ; 2020 :281-284. Publisher's Version
ADobf: Obfuscated Detection Method againstAnalog Trojans on I2C Master-Slave Interface, in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'20). Springfield, MA, USA: IEEE ; 2020 :1064-1067. Publisher's Version
Blurring Boundaries: A New Way to Secure Approximate Computing Systems, in Great Lakes Symposium on VLSI (GLSVLSI'20). Beijing, China: ACM ; 2020. Publisher's Version
Zhang Z, Dofe J, Yu Q. Improving Power Analysis Attack Resistance using Intrinsic Noise in 3D ICs. Integration, the VLSI Journal [Internet]. 2020;73 :30-42. Publisher's Version
Yellu P, Yu Q. Can We Securely Use Approximate Computing?. The 2020 IEEE International Symposium on Circuits & Systems. 2020.
Zhang Z, Yu Q. Invariance Checking Based Trojan Detection Method for Three-Dimensional Integrated Circuits. The 2020 IEEE International Symposium on Circuits & Systems. 2020.
Yellu P, Monjur M, Kammerer TB, Xu D, Yu Q. Security Threats and Countermeasures for Approximate Arithmetic Computing, in ASP-DAC 2020. Beijing, China: IEEE ; 2020 :259-264.
Wang J, Zhang Y, Wang P, Zhicun L, Xue X, Zeng X, Yu Q. An Orthogonal Algorithm for Key Management in Hardware Obfuscation, in AsianHOST'19. Xi'an, China ; 2019. Publisher's Version
Yellu P, Zhang Z, Monjur MMR, Abeysinghe R, Yu Q. Emerging Applications of 3D Integration and Approximate Computing in High-Performance Computing Systems: Unique Security Vulnerabilities, in 2019 IEEE High Performance Extreme Computing Conference (HPEC ‘19). Waltham, MA, USA: IEEE ; 2019. Publisher's Version hpec2019.pdf
Yellu P, Boskov N, Kinsy MA, Yu Q. Security Threats in Approximate Computing Systems, in The ACM Great Lakes Symposium on VLSI (GLSVLSI), 2019. Tysons Corner, VA, USA ; 2019 :387-392. Publisher's Version
Zhang Z, Yu Q. Modeling Hardware Trojans in 3D ICs, in IEEE Symposium on VLSI (ISVLSI) 2019. Miami, FL ; 2019 :483-488. isvlsipublishedversion.pdf
Zhang Y, Pan Z, Wang P, Yu Q. A 0.1-pJ/b and ACF<0.04 Multiple-valued PUF for Chip Identification Using Bit-line Sharing Strategy in 65nm CMOS. IEEE Trans. on Very Large Scale Integr. (VLSI) Syst. [Internet]. 2019. Publisher's Version