Publications

2019
Zhang Z, Njilla L, Kamhoua CA, Yu Q. Thwarting Security Threats from Malicious FPGA Tools with Novel FPGA-Oriented Moving Target Defense (FOMTD). IEEE Transactions on Very Large Scale Integration (VLSI) Systems [Internet]. 2019;27 (3) :665 - 678. Publisher's Version 08551286.pdf
2018
Zhang Z, Yu Q. Towards Energy-Efficient and Secure Computing Systems. Journal of Low Power Electronics and Applications [Internet]. 2018;8 (48) :1-15. Publisher's VersionAbstract

 Countermeasures against diverse security threats typically incur noticeable hardware cost and power overhead, which may become the obstacle for those countermeasures to be applicable in energy-efficient computing systems. This work presents a summary of energy-efficiency techniques that have been applied in security primitives or mechanisms to ensure computing systems’ resilience against various security threats on hardware. This work also uses examples to discuss practical methods for securing the hardware for computing systems to achieve energy efficiency.

jlpea-08-00048.pdf
Zhang Z, Yu Q. A Survey on Energy Efficiency Techniques for Secure Computing Systems. The 9th international green and sustainable computing conference. 2018.
Bu L, Dofe J, Yu Q, Kinsy M. SRASA: a Generalized Theoretical Framework for Security and Reliability Analysis in Computing Systems. Journal of Hardware and Systems Security. 2018 :1-19. bu2018_article_srasaageneralizedtheoreticalfr.pdf
Dofe J, Yu Q. Exploiting PDN Noise to Thwart Correlation Power Analysis Attacks in 3D ICs, in Proceedings of the 20th System Level Interconnect Prediction Workshop. New York, NY, USA: ACM ; 2018 :6:1–6:6. Publisher's Version
Zhang Z, Yu Q. Exploiting Principle of Moving Target Defense to Secure FPGA Systems, in 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). ; 2018 :393-398.
Zhang Z, Yu Q, Njilla L, Kamhoua C. FPGA-oriented moving target defense against security threats from malicious FPGA tools, in 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). ; 2018 :163-166.
Yu Q, Zhang Z, Dofe J. Investigating Reliability and Security of Integrated Circuits and Systems, in 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). ; 2018 :106-111.
Zhang Z, Njilla L, Kamhoua C, Kwiat K, Yu Q. Securing FPGA-based obsolete component replacement for legacy systems, in 2018 19th International Symposium on Quality Electronic Design (ISQED). ; 2018 :401-406.
Yan C, Dofe J, Kontak S, Yu Q, Salman E. Hardware-Efficient Logic Camouflaging for Monolithic 3-D ICs. IEEE Transactions on Circuits and Systems II: Express Briefs. 2018;65 (6) :799-803.
Yuejun Z, Dailu D, Zhao P, Pengjun W, Qiaoyan Y. An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process. Microelectronics Journal. 2018;78 :26-34.
Dofe J, Yu Q. Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation. Trans. Comp.-Aided Des. Integ. Cir. Sys. [Internet]. 2018;37 (2) :273–285. Publisher's Version
2017
Dofe J, Yu Q. Analyzing security vulnerabilities of three-dimensional integrated circuits, in 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). ; 2017 :156-156.
Yu Q, Dofe J, Zhang Z. Exploiting hardware obfuscation methods to prevent and detect hardware Trojans, in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS). ; 2017 :819-822.
Dofe J, Zhang Z, Yu Q, Yan C, Salman E. Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated Circuits, in Proceedings of the on Great Lakes Symposium on VLSI 2017. New York, NY, USA: ACM ; 2017 :327–332. Publisher's Version
Ansari MR, Miller WT, She C, Yu Q. A low-cost masquerade and replay attack detection method for CAN in automobiles, in 2017 IEEE International Symposium on Circuits and Systems (ISCAS). ; 2017 :1-4.
Kramer S, Zhang Z, Dofe J, Yu Q. Mitigating Control Flow Attacks in Embedded Systems with Novel Built-in Secure Register Bank, in Proceedings of the on Great Lakes Symposium on VLSI 2017. New York, NY, USA: ACM ; 2017 :483–486. Publisher's Version
Dofe J, Gu P, Stow D, Yu Q, Kursun E, Xie Y. Security Threats and Countermeasures in Three-Dimensional Integrated Circuits, in Proceedings of the on Great Lakes Symposium on VLSI 2017. New York, NY, USA: ACM ; 2017 :321–326. Publisher's Version
Frey J, Yu Q. A Hardened Network-on-chip Design Using Runtime Hardware Trojan Mitigation Methods. Integr. VLSI J. [Internet]. 2017;56 (C) :15–31. Publisher's Version
2016
Pahlevanzadeh H, Dofe J, Yu Q. Assessing CPA resistance of AES with different fault tolerance mechanisms, in 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC). ; 2016 :661-666.

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