Publications

2016
Dofe J, Zhang Y, Yu Q. DSD: A Dynamic State-Deflection Method for Gate-Level Netlist Obfuscation, in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). ; 2016 :565-570.
Dofe J, Frey J, Yu Q. Hardware security assurance in emerging IoT applications, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS). ; 2016 :2050-2053.
Dofe J, Yu Q, Wang H, Salman E. Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs, in Proceedings of the 26th Edition on Great Lakes Symposium on VLSI. New York, NY, USA: ACM ; 2016 :69–74. Publisher's Version
Dofe J, Yan C, Kontak S, Salman E, Yu Q. Transistor-level camouflaged logic locking method for monolithic 3D IC security, in 2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST). ; 2016 :1-6.
Dofe J, Pahlevanzadeh H, Yu Q. A Comprehensive FPGA-Based Assessment on Fault-Resistant AES Against Correlation Power Analysis Attack. J. Electron. Test. [Internet]. 2016;32 (5) :611–624. Publisher's Version
2015
Dofe J, Reed C, Zhang N, Yu Q. Fault-tolerant methods for a new lightweight cipher SIMON, in Sixteenth International Symposium on Quality Electronic Design. ; 2015 :460-464.
Frey J, Yu Q. Exploiting state obfuscation to detect hardware trojans in NoC network interfaces, in 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS). ; 2015 :1-4.
Ansari MR, Yu S, Yu Q. IntelliCAN: Attack-resilient Controller Area Network (CAN) for secure automobiles, in 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS). ; 2015 :233-236.
Dofe J, Frey J, Nsengiyumva P, Yu Q. Investigating power characteristics of memristor-based logic gates and their applications in a security primitive, in 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS). ; 2015 :1-4.
Nsengiyumva P, Yu Q. Investigation of single-event upsets in dynamic logic based flip-flops, in 2015 IEEE International Symposium on Circuits and Systems (ISCAS). ; 2015 :818-821.
Wu K, Liu P, Wang W, Yu Q, Jiang Y. PSS4: Four-Phase Shifted Sinusoid Symbol Signaling for High Speed I/O interconnects. Computers & Electrical Engineering. 2015;51 :104 - 117.
Dofe J, Frey J, Pahlevanzadeh H, Yu Q. Strengthening SIMON Implementation Against Intelligent Fault Attacks. IEEE Embedded Systems Letters. 2015;7 (4) :113-116.
2014
Wu K, Liu P, Yu Q. A novel signaling technique for high-speed wireline backplane transceiver: Four phase-shifted sinusoid symbol (PSS-4), in 2014 IEEE International Symposium on Circuits and Systems (ISCAS). ; 2014 :2141-2144.
Pahlevanzadeh H, Yu Q. Systematic analyses for latching probability of single-event transients, in Fifteenth International Symposium on Quality Electronic Design. ; 2014 :442-449.
Danesh W, Dofe J, Yu Q. Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic. VLSI Des. [Internet]. 2014;2014 :5:5–5:5. Publisher's Version
Pahlevanzadeh H, Yu Q. A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients. Journal of Electronic Testing. 2014;30 :595-609.
2013
Yu Q, Stock D. Collaborative error control method for sequential logic circuits, in 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). ; 2013 :785-788.
Yu Q, Frey J. Exploiting error control approaches for Hardware Trojans on Network-on-Chip links, in 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS). ; 2013 :266-271.
Zhang T, Yu Q. A fully integrated video digital-to-analog converter with minimized gain error, in 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). ; 2013 :837-840.
Yu Q, Zhang M, Ampadu P. Addressing Network-on-chip Router Transient Errors with Inherent Information Redundancy. ACM Trans. Embed. Comput. Syst. [Internet]. 2013;12 (4) :105:1–105:21. Publisher's Version

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