Advanced manufacturing is transitioning into automated production, which enables the remote system monitoring, increases the online system configuration, and thus reduces the overall cost on workforce. However, the remote access to production plants makes advanced manufacturing vulnerable to various security attacks from physical devices to cyber space. It is imperative to perform holistic assessment on the emerging security vulnerabilities in advanced manufacturing network. As the long-range wide-area network (LoRaWAN) is commonly applied in advanced manufacturing sites, we examine the security weaknesses in commercial LoRa nodes, gateways, and LoRaWAN connection in this project. Jamming attack, replay attack, and man-in-the-middle attack from physical and cyber access will be analyzed. This project will disclose the security vulnerabilities in LoRaWAN and has great potential to facilitate the development of effective defense methods for advanced manufacturing industries.
Approximate Computing (AC) techniques trade accuracy for performance improvement and energy efficiency, being increasingly attractive in various computation-intensive applications such as imaging processing, audio recognition, information search, and artificial intelligence. However, recent literature indicates that the utilization of AC techniques may raise new and unique security concerns. This project investigates hardware (HW) and software (SW) integrated methods to secure AC systems.
The untrusted parties in the global supply chain may tamper with the original design and/or introduce malicious components known as hardware Trojans. As the measurable changes (e.g., delay, power, area, and temperature) introduced by hardware Trojans become relatively small compared with the overall system-under-attack characteristics, side-channel analysis based Trojan detection lose their efficacy. Moreover, the lack of a golden reference model makes Trojan detection difficult. To tackle these emerging challenges, we propose to obfuscate the hardware design at multiple abstraction levels.
Countermeasures for cryptographic devices to thwart side-channel analysis attack and fault attack are typically investigated in a separate fashion. There lacks thorough investigation on how one countermeasure specifically for one attack affects the efficiency of another attack. We are developing a unified countermeasure to address the combined attack. Our research team explores a unified framework to tackle both attacks effecitvely.
New hardware security threats occur in emerging three-dimensional (3D) integrated circuits (ICs). It is imperative to study the potential countermeasures for 3D ICs.
- We are investigating the security vulnerability of 3D ICs while considering different attack models across the IC supply chain.
- We are developing 3D-specific countermeasures at the layout, circuit, and architecture levels to produce trustworthy 3D ICs without relying a trusted foundry.
Cyber-physical systems are prone to security attacks from their limited resources available for self-protection and unsafe language typically used for application programming.
- Control flow attack (CFA) is one of the most common exploitations for embedded systems. Since software based solutions need compiler support and may result in significant performance degradation, we are investigating the architecture level soultion, which is transparent to control flow attackers (who can only manipulate software and firmware).
- At system-level, my research team is developing countermeasures to thwart security threats in automobiles, which are not isolated nodes in the cyber-physical system. Controller Area Network (CAN) is the main bus that connects Electronic Control Units(ECUs) in automobiles. Although CAN protocols have been revised to improve the vehicle safety, the security of CAN is still a concern. This project specifically addresses masquerade and replay attacks on the hardware implementation of CAN systems.
As billions of transistors are integrated on a single die, Networks-on-Chip (NoCs) emerge as an efficient on-chip communication infrastructure. To complement the firmware and software level methods for rogue NoCs detection, we are investigating mechanisms to harden the NoC hardware design against tampering. We explore methods for the OCP-IP compatible network interface design, and hardware Trojan detection in NoC router.
As the technology scales down to very deep submicron the vulnerability of integrated circuits to soft errors increase remarkably. Soft errors caused by high energy particles striking the substrate of integrated circuits increase as the chip density, clock frequency, and voltage supply change due to technology development. Therefore, fault-tolerance mechanisms become more essential in both combinational and sequential circuits. The goal for fault-tolerant designs is achieving a reliable system by detecting soft errors while reducing the area and power consumption.